The present invention relates to a semiconductor device and, more particularly, to a read only memory (ROM) circuit configuration.
A new type of ROM circuit system has been designed and is known as a matrix type ratioless ROM circuit and is characterized in that a plurality of insulated gate field effect transistors (FETs) with source, drain and gate electrodes are arrayed in a matrix on a single semiconductor substrate in order that the plurality of FETs of each column are serially connected through their source and drain paths to a certain output line, as referred to in Kawagoe, U.S. Pat. No. 4,145,701 issued Mar. 20, 1979, entitled "SEMICONDUCTOR DEVICE", the disclosure of which is incorporated herein by reference.
In the conventional matrix type ROM circuit system as disclosed in that patent, careful and great attention was not directed to connection of the matrix type ROM circuits with its peripheral circuit such as a selection circuit for selecting bit lines of the ROM matrix circuit so that integration density of the ROM circuit and access speed for a large memory capacity ROM circuit are insufficient.